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1 mhz to 10 ghz, 62 db dual log detector/controller ADL5519 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2009 analog devices, inc. all rights reserved. features wide bandwidth: 1 mhz to 10 ghz dual-channel and channel difference output ports integrated accurate scaled temperature sensor 62 db dynamic range (3 db) >50 db with 1 db up to 8 ghz stability over temperature: 0.5 db (?40 o c to +85 o c) low noise detector/controller outputs pulse response time: 6 ns/8 ns (fall time/rise time) supply operation: 3.3 v to 5.5 v @ 60 ma fabricated using high speed sige process small footprint, 5 mm 5 mm, 32-lead lfcsp operating temperature range: ?40 o c to +125 o c applications rf transmitter power amplifier linearization and gain/power control power monitoring in radio link transmitters dual-channel wireless infrastructure radios antenna vswr monitor rssi measurement in base stations, wlan, wimax, radar functional block diagram channel a log detector channel b log detector 1 2 3 4 5 6 7 8 comr vstb clpb vlvl vref adjb vpsb comr 24 23 22 21 20 19 18 17 com r vsta clpa temp vpsr adja vpsa com r 25 26 27 28 29 30 31 32 inha inhb inlb comr comr pwdn comr inla 16 15 14 13 12 11 10 9 nc nc outb fbkb outn outp fbka outa bias temp outa outb ADL5519 06198-001 figure 1. general description the ADL5519 is a dual-demodulating logarithmic amplifier that incorporates two ad8317 s. it can accurately convert an rf input signal into a corresponding decibel-scaled output. the ADL5519 provides accurately scaled, independent, logarithmic output volt- ages for both rf measurement channels. the device has two additional output ports, outp and outn, that provide the measured differences between the outa and outb channels. the on-chip channel matching makes the log amp outputs insensitive to temperature and process variations. the temperature sensor pin provides a scaled voltage that is proportional to the temperature over the operating temperature range of the device. the ADL5519 maintains accurate log conformance for signals from 1 mhz to 8 ghz and provides useful operation to 10 ghz. the 3 db dynamic range is typically 62 db and has a 1 db dynamic range of >50 db (re: 50 ). the ADL5519 has a response time of 6 ns/8 ns (fall time/rise time) that enables rf burst detec- tion to a pulse rate of greater than 50 mhz. the device provides unprecedented logarithmic intercept stability vs. ambient temperature conditions. a supply of 3.3 v to 5.5 v is required to power the device. current consumption is typically 60 ma, and it decreases to less than 1 ma when the device is disabled. the device is capable of supplying four log amp measurements simultaneously. linear-in-db measurements are provided at outa and outb with conveniently scaled slopes of ?22 mv/db. the log amp difference between outa and outb is available as differ- ential or single-ended signals at outp and outn. an optional voltage applied to vlvl provides a common-mode reference level to offset outp and outn above ground. the broadband output pins can support many system solutions. any of the ADL5519 output pins can be configured to provide a control voltage to a variable gain amplifier (vga). special attention has been paid to minimize the broadband noise of the output pins so that they can be used for controller applications. the ADL5519 is fabricated on a sige bipolar ic process and is available in a 5 mm 5 mm, 32-lead lfcsp with an operating temperature range of ?40c to +125c.
ADL5519 rev. a | page 2 of 40 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 9 ? esd caution .................................................................................. 9 ? pin configuration and function descriptions ........................... 10 ? typical performance characteristics ........................................... 11 ? theory of operation ...................................................................... 19 ? using the ADL5519 ........................................................................ 20 ? basic connections ...................................................................... 20 ? input signal coupling ................................................................ 20 ? temperature sensor interface ................................................... 22 ? vref interface ........................................................................... 22 ? power-down interface ............................................................... 22 ? setpoint interfacevsta, vstb ............................................. 22 ? output interfaceouta, outb ............................................ 22 ? difference outputoutp, outn ......................................... 23 ? description of characterization ............................................... 23 ? basis for error calculations ...................................................... 23 ? device calibration ..................................................................... 24 ? adjusting accuracy through choice of calibration points...... 24 ? temperature compensation adjustment................................ 25 ? altering the slope ....................................................................... 26 ? channel isolation ....................................................................... 26 ? output filtering .......................................................................... 27 ? package considerations ............................................................. 27 ? operation above 8 ghz ............................................................ 27 ? applications information .............................................................. 28 ? measurement mode ................................................................... 28 ? controller mode ......................................................................... 28 ? automatic gain control ............................................................ 30 ? gain-stable transmitter/receiver ............................................ 32 ? measuring vswr ....................................................................... 34 ? evaluation board ............................................................................ 36 ? configuration options .............................................................. 36 ? evaluation board schematic and artwork ............................. 37 ? outline dimensions ....................................................................... 39 ? ordering guide .......................................................................... 39 ? revision history 4/09rev. 0 to rev. a changes to table 5 .......................................................................... 36 changes to figure 72 ...................................................................... 37 1/08revision 0: initial version
ADL5519 rev. a | page 3 of 40 specifications supply voltage, v p = vpsr = vpsa = vpsb = 5 v, c lpf = 1000 pf, t a = 25c, 50 termination resistor at inha, inhb, unless otherwise noted. table 1. parameter conditions min typ max unit signal input interface inha, inhb (pin 25, pin 32) specified frequency range 0.001 10 ghz dc common-mode voltage v p ? 0.7 v measurement mode, 100 mhz operation adja (pin 21) = 0.65 v, adjb (pin 4) = 0.7 v; outa, outb (pin 15, pin 10) shorted to vsta, vstb (pin 17, pin 8); outp, outn (pin 13, pin 12) shorted to fbka, fbkb (pin 14, pin 11), respectively; sinusoidal input signal; error referred to best-fit line using linear regression between p inha , p inhb = ?40 dbm and ?10 dbm input impedance 1670||0.47 ||pf outa, outb 1 db dynamic range 51 db ?40c < t a < +85c 42 db outa, outb maximum input level 1 db error ?1 dbm outa, outb minimum input level 1 db error ?52 dbm outa, outb, outp, outn slope 1 ?22 mv/db outa, outb intercept 1 22 dbm output voltage (high power in) outa, outb @ p inha , p inhb = ?16 dbm 0.7 v output voltage (low power in) outa, outb @ p inha , p inhb = ?40 dbm 1.37 v outp, outn dynamic gain range 1 db error 50 db ?40c < t a < +85c 44 db temperature sensitivity deviation from outa, outb @ 25c ?40c < t a < +85c, p inha , p inhb = ?16 dbm 0.25 db 25c < t a < 85c, p inha , p inhb = ?40 dbm +0.16 db ?40c < t a < +25c, p inha , p inhb = ?40 dbm ?0.6 db distribution of outp, outn from 25c 25c < t a < 85c, p inha = ?16 dbm, p inhb = ?30 dbm, typical error = ?0.09 db 0.25 db ?40c < t a < +25c, p inha = ?16 dbm, p inhb = ?30 dbm, typical error = 0.25 db 0.4 db 25c < t a < 85c, p inha = ?40 dbm, p inhb = ?30 dbm, typical error = 0.05 db 0.25 db ?40c < t a < +25c, p inha = ?40 dbm, p inhb = ?30 dbm, typical error = ?0.23 db 0.45 db input a-to-input b isolation 80 db input a-to-outb isolation frequency separation = 1 khz, p inha = ?50 dbm, p inha C p inhb when outb/slope = 1 db 60 db input b-to-outa isolation frequency separation = 1 khz, p inhb = ?50 dbm, p inhb C p inha when outa/slope = 1 db 60 db measurement mode, 900 mhz operation adja = 0.6 v, adjb = 0.65 v; outa, outb shorted to vsta, vstb; outp, outn shorted to fbka, fbkb, respectively; sinusoidal input signal; error referred to best fit line using linear regression between p inha , p inhb = ?40 dbm and ?10 dbm input impedance 925||0.54 ||pf outa, outb 1 db dynamic range 54 db ?40c < t a < +85c 49 db outa, outb maximum input level 1 db error ?2 dbm outa, outb minimum input level 1 db error ?56 dbm outa, outb, outp, outn slope 1 ?22 mv/db outa, outb intercept 1 20.3 dbm output voltage (high power in) outa, outb @ p inha , p inhb = ?10 dbm 0.67 v output voltage (low power in) outa, outb @ p inha , p inhb = ?40 dbm 1.34 v
ADL5519 rev. a | page 4 of 40 parameter conditions min typ max unit outp, outn dynamic gain range 1 db error 55 db ?40c < t a < +85c 48 db temperature sensitivity deviation from outa, outb @ 25c ?40c < t a < +85c, p inha , p inhb = ?16 dbm 0.25 db 25c < t a < 85c, p inha , p inhb = ?40 dbm +0.25 db ?40c < t a < +25c, p inha , p inhb = ?40 dbm ?0.5 db distribution outp, outn from 25c 25c < t a < 85c, p inha = ?16 dbm, p inhb = ?30 dbm, typical error = ?0.08 db 0.25 db ?40c < t a < +25c, p inha = ?16 dbm, p inhb = ?30 dbm typical error = 0.3 db 0.4 db 25c < t a < 85c, p inha = ?40 dbm, p inhb = ?30 dbm, typical error = 0.17 db 0.25 db ?40c < t a < +25c, p inha = ?40 dbm, p inhb = ?30 dbm, typical error = ?0.19 db 0.4 db input a-to-input b isolation 75 db input a-to-outb isolation frequency separation = 1 khz, p inha = ?50 dbm, p inha C p inhb when outb/slope = 1 db 50 db input b-to-outa isolation frequency separation = 1 khz, p inhb = ?50 dbm, p inhb C p inha when outa/slope = 1 db 50 db measurement mode, 1.9 ghz operation adja = 0.5 v, adjb = 0.55 v; outa, outb shorted to vsta, vstb; outp, outn shorted to fbka, fbkb, respectively; sinusoidal input signal; error referred to best fit line using linear regression between p inha , p inhb = ?40 dbm and ?10 dbm input impedance 525||0.36 ||pf outa, outb 1 db dynamic range 55 db ?40c < t a < +85c 49 db outa, outb maximum input level 1 db error ?4 dbm outa, outb minimum input level 1 db error ?59 dbm outa, outb, outp, outn slope 1 ?22 mv/db outa, outb intercept 1 18 dbm output voltage (high power in) outa, outb @ p inha , p inhb = ?10 dbm 0.62 v output voltage (low power in) outa, outb @ p inha , p inhb = ?40 dbm 1.28 v outp, outn dynamic gain range 1 db error 55 db ?40c < t a < +85c 48 db temperature sensitivity deviation from outa, outb @ 25c ?40c < t a < +85c, p inha , p inhb = ?16 dbm 0.2 db 25c < t a < 85c, p inha , p inhb = ?40 dbm +0.25 db ?40c < t a < +25c, p inha , p inhb = ?40 dbm ?0.5 db distribution of outp, outn from 25c 25c < t a < 85c, p inha = ?16 dbm, p inhb = ?30 dbm, typical error = ?0.07 db 0.3 db ?40c < t a < +25c, p inha = ?16 dbm, p inhb = ?30 dbm, typical error = 0.23 db 0.4 db 25c < t a < 85c, p inha = ?40 dbm, p inhb = ?30 dbm, typical error = 0.16 db 0.3 db ?40c < t a < +25c, p inha = ?40 dbm, p inhb = ?30 dbm, typical error = ?0.22 db 0.4 db input a-to-input b isolation 65 db input a-to-outb isolation frequency separation = 1 khz, p inha = ?50 dbm, p inha C p inhb when outb/slope = 1 db 46 db input b-to-outa isolation frequency separation = 1 khz, p inhb = ?50 dbm, p inhb C p inha when outa/slope = 1 db 46 db
ADL5519 rev. a | page 5 of 40 parameter conditions min typ max unit measurement mode, 2.2 ghz operation adja = 0.48 v, adjb = 0.6 v; outa, outb shorted to vsta, vstb; outp, outn shorted to fbka, fbkb, respectively; sinusoidal input signal; error referred to best fit line using linear regression between p inha , p inhb = ?40 dbm and ?10 dbm input impedance 408||0.34 ||pf outa, outb 1 db dynamic range 55 db ?40c < t a < +85c 50 db outa, outb maximum input level 1 db error ?5 dbm outa, outb minimum input level 1 db error ?60 dbm outa, outb, outp, outn slope 1 ?22 mv/db outa, outb intercept 1 16.9 dbm output voltage (high power in) outa, outb @ p inha , p inhb = ?10 dbm 0.6 v output voltage (low power in) outa, outb @ p inha , p inhb = ?40 dbm 1.26 v outp, outn dynamic gain range 1 db error 56 db ?40c < t a < +85c 40 db temperature sensitivity deviation from outa, outb @ 25c ?40c < t a < +85c, p inha , p inhb = ?16 dbm 0.28 db 25c < t a < 85c, p inha , p inhb = ?40 dbm +0.3 db ?40c < t a < +25c, p inha , p inhb = ?40 dbm ?0.5 db distribution of outp, outn from 25c 25c < t a < 85c, p inha = ?16 dbm, p inhb = ?30 dbm, typical error = ?0.07 db 0.25 db ?40c < t a < +25c, p inha = ?16 dbm, p inhb = ?30 dbm, typical error = 0.25 db 0.4 db 25c < t a < 85c, p inha = ?40 dbm, p inhb = ?30 dbm, typical error = 0.17 db 0.25 db ?40c < t a < +25c, p inha = ?40 dbm, p inhb = ?30 dbm typical error = ?0.22db 0.4 db input a-to-input b isolation 60 db input a-to-outb isolation frequency separation = 1 khz, p inha = ?50 dbm, p inha C p inhb when outb/slope = 1 db 46 db input b-to-outa isolation frequency separation = 1 khz, p inhb = ?50 dbm, p inhb C p inha when outa/slope = 1 db 46 db measurement mode, 3.6 ghz operation adja = 0.35 v adjb = 0.42; outa, outb shorted to vsta, vstb; outp, outn shorted to fbka, fbkb, respectively; sinusoidal input signal; error referred to best fit line using linear regression between p inha , p inhb = ?40 dbm and ?10 dbm input impedance 187||0.66 ||pf outa, outb 1 db dynamic range 54 db ?40c < t a < +85c 44 db outa, outb maximum input level 1 db error ?4 dbm outa, outb minimum input level 1 db error ?58 dbm outa, outb, outp, outn slope 1 ?22.5 mv/db outa, outb intercept 1 17 dbm output voltage (high power in) outa, outb @ p inha , p inhb = ?10 dbm 0.62 v output voltage (low power in) outa, outb @ p inha , p inhb = ?40 dbm 1.31 v outp, outn dynamic gain range 1 db error 52 db ?40c < t a < +85c 42 db
ADL5519 rev. a | page 6 of 40 parameter conditions min typ max unit temperature sensitivity deviation from outa, outb @ 25c ?40c < t a < +85c, p inha , p inhb = ?16 dbm 0.4 db 25c < t a < 85c, p inha , p inhb = ?40 dbm +0.6 db ?40c < t a < +25c, p inha , p inhb = ?40 dbm ?0.45 db distribution of outp, outn from 25c 25c < t a < 85c, p inha = ?16 dbm, p inhb = ?30 dbm, typical error = ?0.07 db 0.25 db ?40c < t a < +25c, p inha = ?16 dbm, p inhb = ?30 dbm, typical error = 0.27 db 0.45 db 25c < t a < 85c, p inha = ?40 dbm, p inhb = ?30 dbm, typical error = 0.31 db 0.3 db ?40c < t a < +25c, p inha = ?40 dbm, p inhb = ?30 dbm, typical error = ?0.14 db 0.5 db input a-to-input b isolation 40 db input a-to-outb isolation frequency separation = 1 khz, p inha = ?50 dbm, p inha C p inhb when outb/slope = 1 db 20 db input b-to-outa isolation frequency separation = 1 khz, p inhb = ?50 dbm, p inhb C p inha when outa/slope = 1 db 20 db measurement mode, 5.8 ghz operation adja = 0.58 v, adjb = 0.7 v; outa, outb shorted to vsta, vstb; outp, outn shorted to fbka, fbkb respectively; sinusoidal input signal; error referred to best fit line using linear regression between p inha , p inhb = ?40 dbm and ?20 dbm input impedance 28||1.19 ||pf outa, outb 1 db dynamic range 53 db ?40c < t a < +85c 45 db outa, outb maximum input level 1 db error ?2 dbm outa, outb minimum input level 1 db error ?55 dbm outa, outb, outp, outn slope 1 ?22.5 mv/db outa, outb intercept 1 20 dbm output voltage (high power in) outa, outb @ p inha , p inhb = ?10 dbm 0.68 v output voltage (low power in) outa, outb @ p inha , p inhb = ?40 dbm 1.37 v outp, outn dynamic gain range 1 db error 53 db ?40c < t a < +85c 46 db temperature sensitivity deviation from outa, outb @ 25c ?40c < t a < +85c, p inha , p inhb = ?16dbm 0.25 db 25c < t a < 85c, p inha , p inhb = ?40 dbm +0.25 db ?40c < t a < +25c, p inha , p inhb = ?40 dbm ?0.4 db distribution of outp, outn from 25c 25c < t a < 85c, p inha = ?16 dbm, p inhb = ?30 dbm, typical error = 0.02 db 0.3 db ?40c < t a < +25c, p inha = ?16 dbm, p inhb = ?30 dbm, typical error = 0.25 db 0.4 db 25c < t a < 85c, p inha = ?40 dbm, p inhb = ?30 dbm, typical error = 0.13 db 0.3 db ?40c < t a < +25c, p inha = ?40 dbm, p inhb = ?30 dbm, typical error = 0.06 db 0.5 db input a-to-input b isolation 45 db input a-to-outb isolation frequency separation = 1 khz, p inha = ?50 dbm, p inha C p inhb when outb/slope = 1 db 48 db input b-to-outa isolation frequency separation = 1 khz, p inhb = ?50 dbm, p inhb C p inha when outa/slope = 1 db 48 db
ADL5519 rev. a | page 7 of 40 parameter conditions min typ max unit measurement mode, 8 ghz operation adja = 0.72 v, adjb = 0.82 v to gnd; outa, outb shorted to vsta, vstb; outp, outn shorted to fbka, fbkb, respectively; sinusoidal input signal; error referred to best fit line using linear regression between p inha , p inhb = ?40 dbm and ?20 dbm input impedance +10||?1.92 ||pf outa, outb 1 db dynamic range 48 db ?40c < t a < +85c 38 db outa, outb maximum input level 1 db error 0 dbm outa, outb minimum input level 1 db error ?48 dbm outa, outb, outp, outn slope 1 ?22 mv/db outa, outb intercept 1 26 dbm output voltage (high power in) outa, outb @ p inha , p inhb = ?10 dbm 0.81 v output voltage (low power in) outa, outb @ p inha , p inhb = ?40 dbm 1.48 v outp, outn dynamic gain range 1 db error 50 db ?40c < t a < +85c 42 db temperature sensitivity deviation from outa, outb @ 25c ?40c < t a < +85c, p inha , p inhb = ?16 dbm 0.4 db 25c < t a < 85c, p inha , p inhb = ?40 dbm ?0.1 db ?40c < t a < +25c, p inha , p inhb = ?40 dbm +0.5 db distribution of outp, outn from 25c 25c < t a < 85c, p inha = ?16 dbm, p inhb = ?30 dbm, typical error = 0.2db 0.3 db ?40c < t a < +25c, p inha = ?16 dbm, p inhb = ?30 dbm, typical error = 0.09db 0.5 db 25c < t a < 85c, p inha = ?40 dbm, p inhb = ?30 dbm, typical error = ?0.07db 0.3 db ?40c < t a < +25c, p inha = ?40 dbm, p inhb = ?30 dbm, typical error = 0.17 db 0.5 db input a-to-input b isolation 45 db input a-to-outb isolation frequency separation = 1 khz, p inha = ?50 dbm, p inha C p inhb when outb/slope = 1 db 30 db input b-to-outa isolation frequency separation = 1 khz, p inhb = ?50 dbm, p inhb C p inha when outa/slope = 1 db 30 db output interface outa, outb; outp, outn outa, outb voltage range vsta, vstb = 1.7 v, rf in = open 0.3 v vsta, vstb = 0 v, rf in = open v p ? 0.4 v outp, outn voltage range fbka, fbkb = open and outa < outb, r l 240 to ground 0.09 v fbka, fbkb = open and outa > outb, r l 240 to ground v p ? 0.15 v source/sink current output held at 1 v to 1% change 10 ma capacitance drive 1 nf output noise inha, inhb = 2.2 ghz, ?10 dbm, f noise = 100 khz, clpa, clpb = open 10 nv/hz fall time input level = no signal to ?10 dbm, 80% to 20%, clpa, clpb = 10 pf 12 ns input level = no signal to ?10 dbm, 80% to 20%, clpa, clpb = open 6 ns rise time input level = ?10 dbm to no signal, 20% to 80%, clpa, clpb = 10 pf 16 ns input level = ?10 dbm to no signal, 20% to 80%, clpa, clpb = open 8 ns video bandwidth (or envelope bandwidth) 10 mhz setpoint interface vsta, vstb nominal input range input level = 0 dbm, measurement mode 0.38 v input level = C50 dbm, measurement mode 1.6 v input resistance controller mode, sourcing 50 a 40 k
ADL5519 rev. a | page 8 of 40 parameter conditions min typ max unit difference level adjust vlvl (pin 6) input voltage outp, outn = fbka, fbkb v p ? 1 v input resistance outp, outn = fbka, fbkb 100 k temperature compensation adja, adjb input resistance adja, adjb = 0.9 v, sourcing 50 a 13 k disable threshold voltage adja, adjb = open v p ? 0.4 v voltage reference vref (pin 5) output voltage 1.15 v temperature sensitivity ?40c < t a < +25c; relative t a = 25c +26 v/c 25c < t a < 85c; relative t a = 25c ?26 v/c current limit source/sink 3/3 ma temperature reference temp (pin 19) output voltage 1.36 v temperature sensitivity ?40c < t a < +125c 4.5 mv/c current limit source/sink 4/50 ma/a power-down interface pwdn (pin 28) logic level to enable logic low enables 0 v logic level to disable logic high disables v p ? 0.2 v input current logic high pwdn = 5 v 2 a logic low pwdn = 0 v 20 a enable time pwdn low to outa, outb at 100% final value, clpa, clpb = open, rf in = ?10 dbm 0.4 s disable time pwdn high to outa, outb at 10% final value, clpa, clpb = open, rf in = 0 dbm 0.25 s power interface vpsa, vpsb, vpsr supply voltage 3.3 5.5 v quiescent current 60 ma vs. temperature ?40c t a +85c 147 a/c disable current adja, adjb = pwdn = v p <1 ma 1 slope and intercept are determined by calculating the best-fit line between the power levels of ?40 dbm and ?10 dbm at the spe cified input frequency.
ADL5519 rev. a | page 9 of 40 absolute maximum ratings table 2. parameter rating supply voltage: vpsa, vpsb, vpsr 5.7 v v set voltage: vsta, vstb 0 to v p input power (single-ended, re: 50 ) inha, inla, inhb, inlb 12 dbm internal power dissipation 420 mw ja 42c/w maximum junction temperature 142c operating temperature range ?40c to +125c storage temperature range ?65c to +150c lead temperature (soldering, 60 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ADL5519 rev. a | page 10 of 40 pin configuration and fu nction descriptions pin 1 indicator nc = no connect 1 comr 2 comr 3 vpsb 4 adjb 5 vref 6 vlvl 7 clpb 8 vstb 24 comr ADL5519 23 comr 22 vpsa 21 adja 20 vpsr 19 temp 18 clpa 17 vsta 9 n c 1 0 o u t b 1 1 f b k b 1 2 o u t n 1 3 o u t p 1 4 f b k a 1 5 o u t a 1 6 n c 3 2 i n h b 3 1 i n l b 3 0 c o m r 2 9 c o m r 2 8 p w d n 2 7 c o m r 2 6 i n l a 2 5 i n h a top view (not to scale) 06198-002 figure 2. pin configuration table 3. pin function descriptions pin o. nemonic description 1 comr connect via low impedance to common. 2 comr connect via low impedance to common. 3 vpsb positive supply for channel b. apply 3.3 v to 5.5 v supply voltage. 4 adjb dual-function pin: temperature adjust pin for channel b and power-down interface for outb. 5 vref voltage reference (1.15 v). 6 vlvl dc common-mode adjust for difference output. 7 clpb loop filter pin for channel b. 8 vstb setpoint control input for channel b. 9 nc no connect. 10 outb output voltage for channel b. 11 fbkb difference op amp feedback pin for outn op amp. 12 outn difference output (outb ? outa + vlvl). 13 outp difference output (outa ? outb + vlvl). 14 fbka difference op amp feedback pin for outp op amp. 15 outa output voltage for channel a. 16 nc no connect. 17 vsta setpoint control input for channel a. 18 clpa loop filter pin for channel a. 19 temp temperature sensor output (1.3 v with 4.5 mv/c slope). 20 vpsr positive supply for difference outputs and temp erature sensor. apply 3.3 v to 5.5 v supply voltage. 21 adja dual-function pin: temperature adjust pin for channel a and power-down interface for outa. 22 vpsa positive supply for channel a. apply 3.3 v to 5.5 v supply voltage. 23 comr connect via low impedance to common. 24 comr connect via low impedance to common. 25 inha ac-coupled rf input for channel a. 26 inla ac-coupled rf common for channel a. 27 comr connect via low impedance to common. 28 pwdn power-down for difference output and temperature sensor. 29 comr connect via low impedance to common. 30 comr connect via low impedance to common. 31 inlb ac-coupled rf common for channel b. 32 inhb ac-coupled rf input for channel b. paddle internally connected to comr.
ADL5519 rev. a | page 11 of 40 typical performance characteristics v p = 5 v; t a = +25c, ?40c, +85c; clpa, clpb = 1 f. colors: +25c black, ?40c blue, +85c red. 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 output voltage (v) error (db) p in (dbm) 06198-003 figure 3. outa, outb voltage and log conformance vs. input amplitude at 100 mhz, typical device, adja, adjb = 0.65 v, 0.7 v, sine wave, single-ended drive 06198-004 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 error (db) p in (dbm) figure 4. distribution of outa, outb error over temperature after ambient normalization vs. input amplitude for 45 devices, frequency = 100 mhz, adja, adjb = 0.65 v, 0.7 v, sine wave, single-ended drive 06198-005 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outa ? outb (v) p in (dbm) figure 5. distribution of [outa ? outb] voltage difference over temperature for 45 devices from a nominal lot, frequency = 100 mhz, adja, adjb = 0.65 v, 0.7 v, sine wave, single-ended drive 2.0 1.5 1.0 0.5 0 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outn n p outp outp, outn output voltage (v) error (db) p in (dbm) 06198-006 figure 6. outp, outn gain error and voltage vs. input amplitude at 100 mhz, typical device, adja, adjb = 0.65 v, 0.7, sine wave, single-ended drive, p inhb = ?30 dbm, channel a swept 06198-007 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outp ? outn output voltage (v) error (db) p in (dbm) figure 7. distribution of [outp ? ou tn] gain error and voltage vs. input amplitude over temperature, after ambi ent normalization for 45 devices from a nominal lot, frequency = 100 mhz, adja, adjb = 0.65 v, 0.7 v, sine wave, single-ended drive, p inhb = ?30 dbm, channel a swept 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 output voltage (v) error (db) p in (dbm) 06198-008 figure 8. outa, outb voltage and log conformance vs. input amplitude at 900 mhz, typical device, adja, adjb = 0.6 v, 0.65 v, sine wave, single-ended drive
ADL5519 rev. a | page 12 of 40 06198-009 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 error (db) p in (dbm) figure 9. distribution of outa, outb error over temperature after ambient normalization vs. input amplitude for 45 devices, frequency = 900 mhz, adja, adjb = 0.6 v, 0.65 v, sine wave, single-ended drive 06198-010 0.20 0.10 0 ?0.10 ?0.20 0.15 0.05 ?0.05 ?0.15 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outa ? outb (v) p in (dbm) figure 10. distribution of [outa ? outb] voltage difference over temperature for 45 devices from a nominal lot, frequency = 900 mhz, adja, adjb = 0.6 v, 0.65 v, sine wave, single-ended drive 2.0 1.5 0.5 1.0 0 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outp, outn output voltage (v) error (db) p in (dbm) 06198-011 outn n p outp figure 11. outp, outn gain error and voltage vs. input amplitude at 900 mhz, typical device, adja, adjb = 0.6 v, 0.65 v, sine wave, single-ended drive; p inhb = ?30 dbm, channel a swept 06198-012 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outp ? outn output voltage (v) error (db) p in (dbm) figure 12. distribution of [outp ? outn] gain error and voltage vs. input amplitude over temperature, after ambient normalization for 45 devices from a nominal lot, frequency = 900 mhz, adja, adjb = 0.6 v, 0.65 v, sine wave, single-ended drive, p inhb = ?30 dbm, channel a swept 2.0 0 0.5 1.0 1.5 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 output voltage (v) error (db) p in (dbm) 06198-013 figure 13. outa, outb voltage and log conformance vs. input amplitude at 1.9 ghz, typical device, adja, adjb = 0.5 v, 0.55 v, sine wave, single-ended drive 06198-014 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 error (db) p in (dbm) figure 14. distribution of outa, outb error over temperature after ambient normalization vs. input amplitude for 45 devices, frequency = 1.9 ghz, adja, adjb = 0.5 v, 0.55 v, sine wave, single-ended drive
ADL5519 rev. a | page 13 of 40 06198-015 0.20 0.10 0 ?0.10 ?0.20 0.15 0.05 ?0.05 ?0.15 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outa ? outb (v) p in (dbm) figure 15. distribution of [outa C outb] voltage difference over temperature for 45 devices from a nominal lot, frequency = 1.9 ghz, adja, adjb = 0.5 v, 0.55 v, sine wave, single-ended drive 06198-016 2.0 1.5 0.5 1.0 0 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outp, outn output voltage (v) error (db) p in (dbm) outn n p outp figure 16. outp, outn gain error and voltage vs. input amplitude at 1.9 ghz, with b input held at ?30 dbm and a input swept, typical device, adja, adjb = 0.5 v, 0.55 v, sine wave, single-ended drive, p inhb = ?30 dbm, channel a swept 06198-017 2.0 ?1.5 ?0.5 0.5 1.5 ?1.0 0 1.0 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outp ? outn output voltage (v) error (db) p in (dbm) figure 17. distribution of [outp ? outn] gain error and voltage vs. input amplitude over temperature, after ambient normalization for 45 devices from a nominal lot, frequency = 1.9 ghz, adja, adjb = 0.5 v, 0.55 v, sine wave, single-ended drive, p inhb = ?30 dbm, channel a swept 2.0 0 0.5 1.5 1.0 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 output voltage (v) error (db) p in (dbm) 06198-018 figure 18. outa, outb voltage and log conformance vs. input amplitude at 2.2 ghz, typical device, adja, adjb = 0.48 v, 0.6 v, sine wave, single-ended drive 06198-019 2.0 ?2.0 ?1.0 0 1.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 error (db) p in (dbm) figure 19. distribution of outa, outb error over temperature after ambient normalization vs. input amplitude for at least 45 devices from a nominal lot, frequency = 2.2 ghz, adja, adjb = 0.48 v, 0.6 v, sine wave, single-ended drive 06198-020 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.20 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outa ? outb (v) p in (dbm) figure 20. distribution of [outa C outb] voltage difference over temperature for 45 devices from a nominal lot, frequency = 2.2 ghz, adja, adjb = 0.48 v, 0.6 v, sine wave, single-ended drive
ADL5519 rev. a | page 14 of 40 06198-021 2.0 1.5 0.5 1.0 0 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outp, outn output voltage (v) error (db) p in (dbm) outn n p outp figure 21. outp, outn gain error and voltage vs. input amplitude at 2.2 ghz, typical device, adja, adjb = 0.48 v, 0.6 v, sine wave, single-ended drive, p inhb = ?30 dbm, channel a swept 06198-022 2.0 ?1.5 ?0.5 0.5 1.5 ?1.0 0 1.0 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outp ? outn output voltage (v) error (db) p in (dbm) figure 22. distribution of [outp ? outn] gain error and voltage vs. input amplitude over temperature, after ambient normalization for 45 devices from a nominal lot, frequency = 2.2 ghz, adja, adjb = 0.48 v, 0.6 v, sine wave, single-ended drive, p inhb = ?30 dbm, channel a swept 2.0 0 0.5 1.5 1.0 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 output voltage (v) error (db) p in (dbm) 06198-023 figure 23. outa, outb voltage and log conformance vs. input amplitude at 3.6 ghz, typical device, adja, adjb = 0.35 v, 0.42 v, sine wave, single-ended drive 06198-024 2.0 ?2.0 ?1.0 0 1.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 error (db) p in (dbm) figure 24. distribution of outa, outb error over temperature after ambient normalization vs. input amplitude for 45 devices from a nominal lot, frequency = 3.6 ghz, adja, adjb = 0.35 v, 0.42 v, sine wave, single-ended drive 06198-025 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.20 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outa ? outb (v) p in (dbm) figure 25. distribution of [outa C outb] voltage difference over temperature for 45 devices from a nominal lot, frequency = 3.6 ghz, adja, adjb = 0.35 v, 0.42 v, sine wave, single-ended drive 06198-026 2.0 1.5 0.5 1.0 0 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outp, outn output voltage (v) error (db) p in (dbm) outn n p outp figure 26. outp, outn gain error and voltage vs. input amplitude at 3.6 ghz, typical device, adja, adjb = 0.35 v, 0.42 v, sine wave, single-ended drive; p inhb = ?30 dbm, channel a swept
ADL5519 rev. a | page 15 of 40 06198-027 1.5 ?1.5 ?0.5 0.5 ?1.0 0 1.0 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outp ? outn output voltage (v) error (db) p in (dbm) figure 27. distribution of [outp ? outn] gain error and voltage vs. input amplitude over temperature, after ambient normalization for 45 devices from a nominal lot, frequency = 3.6 ghz, adja, adjb = 0.35 v, 0.42 v, sine wave, single-ended drive, p inhb = ?30 dbm, channel a swept 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 output voltage (v) error (db) p in (dbm) 06198-102 figure 28. outa, outb voltage and log conformance vs. input amplitude at 5.8 ghz, typical device, adja, adjb = 0.58 v, 0.7 v, sine wave, single-ended drive 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 error (db) p in (dbm) 06198-101 figure 29. distribution of outa, outb error over temperature after ambient normalization vs. input amplitude for at least 15 devices from multiple lots, frequency = 5.8 ghz, adja, adjb = 0.58 v, 0.7 v, sine wave, single-ended drive 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.20 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outa ? outb (v) p in (dbm) 06198-130 figure 30. distribution of [outa C outb] voltage difference over temperature for 45 devices from a nominal lot, frequency = 5.8 ghz, adja, adjb = 0.58 v, 0.7 v, sine wave, single-ended drive 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outp, outn output voltage (v) error (db) p in (dbm) 06198-131 outn n p outp figure 31. outp, outn gain error and voltage vs. input amplitude at 5.8 ghz, typical device, adja, adjb = 0.58 v, 0.7 v, sine wave, single-ended drive, p inhb = ?30 dbm, channel a swept 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outp ? outn output voltage (v) error (db) p in (dbm) 06198-105 figure 32. distribution of [outp ? outn] gain error and voltage vs. input amplitude over temperature, after ambient normalization for 45 devices from a nominal lot, frequency = 5.8 ghz, adja, adjb = 0.58 v, 0.7 v, sine wave, single-ended drive, p inhb = ?30 dbm, channel a swept
ADL5519 rev. a | page 16 of 40 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 output voltage (v) error (db) p in (dbm) 06198-107 figure 33. outa, outb voltage and log conformance vs. input amplitude at 8 ghz, typical device, adja, adjb = 0.72 v, 0.82 v, sine wave, single-ended drive 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 error (db) p in (dbm) 06198-106 figure 34. distribution of outa, outb error over temperature after ambient normalization vs. input amplitude for 45 devices from a nominal lot, frequency = 8 ghz, adja, adjb = 0.72 v, 0.82 v, sine wave, single-ended drive 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.20 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outa ? outb (v) p in (dbm) 06198-135 figure 35. distribution of [outa ? outb] voltage difference over temperature for 45 devices from a nominal lot, frequency = 8 ghz, adja, adjb = 0.72 v, 0.82 v, sine wave, single-ended drive 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outp, outn output voltage (v) error (db) p in (dbm) 06198-136 outn n p outp figure 36. outp, outn gain error and voltage vs. input amplitude at 8 ghz, typical device, adja, adjb = 0.72 v, 0.82 v, sine wave, single-ended drive, p inhb = ?30 dbm, channel a swept 1.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 2.0 1.0 0 ?1.0 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 outp ? outn output voltage (v) error (db) p in (dbm) 06198-110 figure 37. distribution of [outp ? outn] gain error and voltage vs. input amplitude over temperature, after ambient normalization for 45 devices from a nominal lot, frequency = 8 ghz, adja, adjb = 0.72 v, 0.82 v, sine wave, single-ended drive, p inhb = ?30 dbm, channel a swept 06198-138 0 j2 j1 ?j1 ?j2 3600mhz 3600mhz j0.5 ?j0.5 j0.2 ?j0.2 2 1 0.5 0.2 100mhz 900mhz 1900mhz 2200mhz figure 38. single-ended input impedance (s11) vs. frequency; z o = 50
ADL5519 rev. a | page 17 of 40 1200 1000 800 600 400 200 0 1.12 1.14 1.16 1.18 count vref (v) mean: 1.14986 06198-029 figure 39. distribution of vref pin voltage for 4000 devices 1200 1000 800 600 400 200 0 1.32 1.30 1.34 1.36 1.40 1.38 1.42 count temp (v) mean: 1.36332 06198-030 figure 40. distribution of temp pin voltage for 4000 devices 1.170 1.165 1.160 1.155 1.150 1.145 1.140 1.135 1.130 1.125 1.120 ?40 ?15 10 35 60 85 v ref (v) temperature (c) 06198-141 figure 41. change in vref pin voltage vs. temperature for 45 devices 1k 10k 100k 1m 10m 100m output noise (v/ hz) frequency (hz) 06198-142 inha = 0dbm inhb = 0dbm inha = ?20dbm inhb = ?20dbm inha = ?40dbm inhb = ?40dbm inha = off inhb = off 10 1 100n 10n 1n figure 42. noise spectral density of outa, outb; clpa, clpb = open 1k 10k 100k 1m 10m 100m output noise (v/ hz) frequency (hz) 06198-143 outn, inha = 0dbm outn, inha = ?20dbm outp, inha = 0dbm outp, inha = ?20dbm outn, inha = ?40dbm outn, inha = off outp, inha = ?40dbm outp, inha = off 10 1 100n 10n 1n figure 43. noise spectral density of outp, outn; clpa, clpb = 0.1 f, frequency = 2140 mhz 10 1 100n 10n 1n 1k 10k 100k 1m 10m 100m output noise (v/ hz) frequency (hz) 06198-144 inha = 0dbm inhb = 0dbm inha = ?20dbm inhb = ?20dbm inha = ?40dbm inhb = ?40dbm inha = off inhb = off figure 44. noise spectral density of outa, outb; clpa, clpb = 0.1 f, frequency = 2140 mhz
ADL5519 rev. a | page 18 of 40 06198-145 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 ?6.0 ?5.4 ?4.8 ?4.2 ?3.6 ?3.0 ?2.4 ?1.8 ?1.2 ?0.6 0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 output voltage outa, outb (v) time (ns) inha, inhb = ?10dbm inha, inhb = ?20dbm inha, inhb = ?30dbm inha, inhb = ?40dbm figure 45. output response to rf burst input for various rf input levels, carrier frequency = 900 mhz, clpa = open 06198-146 2.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 ?5 ?3 ?1 1 3 5 7 9 11 13 15 17 19 21 23 25 output voltage outa, outb (v) time (s) inha, inhb = ?10dbm inha, inhb = ?20dbm iinha, inhb = ?30dbm inha, inhb = ?40dbm figure 46. output response to rf burst input for various rf input levels, carrier frequency = 900 mhz, clpa = 0.1 f 06198-147 2.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 22.5 ?2.5 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.6 2.8 2.4 3.0 output voltage outa, outb (v) input voltage pwdn pulse (v) time (s) inha, inhb = 0dbm inha, inhb = ?10dbm inha, inhb = ?20dbm inha, inhb = ?30dbm inha, inhb = ?40dbm rf off pwdn pulse figure 47. output response using power-down mode for various rf input levels, carrier frequency = 900 mhz, clpa = open 06198-148 2.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 22.5 ?2.5 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.6 2.8 2.4 3.0 output voltage outa, outb (v) input voltage pwdn pulse (v) time (s) inha, inhb = 0dbm inha, inhb = ?10dbm inha, inhb = ?20dbm inha, inhb = ?30dbm inha, inhb = ?40dbm pwdn pulse figure 48. output response using power-down mode for various rf input levels, carrier frequency = 900 mhz, clpa = 0.1 f 0.06 0.05 0.04 0.03 0.02 0.01 0 3.03.23.43.63.84.04.24.44.64.85.0 supply current (a) pwdn, adja, adjb voltage (v) 06198-150 decreasing increasing figure 49. supply current vs. v pwdn , v adja , v adjb
ADL5519 rev. a | page 19 of 40 theory of operation the ADL5519 is a dual-channel, six-stage demodulating loga- rithmic amplifier that is specifically designed for use in rf measurement and power control applications at frequencies up to 10 ghz. the ADL5519 is a derivative of the ad8317 logarithmic detector/controller core. the ADL5519 maintains tight intercept variability vs. temperature over a 50 db range. each measurement channel offers performance equivalent to that of the ad8317 . the complete circuit block diagram is shown in figure 50 . 1 2 3 4 5 6 7 8 comr vstb clpb vlvl vref adjb vpsb comr 24 23 22 21 20 19 18 17 com r vsta clpa temp vpsr adja vpsa com r 25 26 27 28 29 30 31 32 inha inhb inlb comr comr pwdn comr inla 16 15 14 13 12 11 10 9 nc nc outb fbkb outn outp fbka outa bias temp outa outb channel a log detector ADL5519 channel b log detector 06198-041 figure 50. block diagram each measurement channel is a full differential design using a proprietary, high speed sige process that extends high frequency performance. figure 51 shows the basic diagram of the channel a signal path; its functionality is identical to that of the channel b signal path. inha inla vsta outa clpa vi vi det det det det 06198-042 figure 51. single channel block diagram the maximum input with 1 db log conformance error is typically ?5 dbm (re: 50 ). the noise spectral density referred to the input is 1.15 nv/hz, which is equivalent to a voltage of 118 v rms in a 10.5 ghz bandwidth or a noise power of ?66 dbm (re: 50 ). this noise spectral density sets the lower limit of the dynamic range. however, the low end accuracy of the ADL5519 is enhanced by specially shaping the demodulating transfer characteristic to partially compensate for errors due to internal noise. the common pins provide a quality, low impedance connection to the printed circuit board (pcb) ground. the package paddle, which is inter- nally connected to the comr pins, should also be grounded to the pcb to reduce thermal impedance from the die to the pcb. the logarithmic function is approximated in a piecewise fashion by six cascaded gain stages. for a more comprehensive explana- tion of the logarithm approximation, refer to the ad8307 data sheet. the cells have a nominal voltage gain of 9 db each, with a 3 db bandwidth of 10.5 ghz. using precision biasing, the gain is stabilized over temperature and supply variations. the overall dc gain is high because of the cascaded nature of the gain stages. an offset compensation loop is included to correct for offsets within the cascaded cells. at the output of each gain stage, a square-law detector cell is used to rectify the signal. the rf signal voltages are converted to a fluctuating differential current, having an average value that increases with signal level. along with the six gain stages and detector cells, an additional detector is included at the input of each measurement channel, providing a 54 db dynamic range in total. after the detector currents are summed and filtered, the following function is formed at the summing node: i d log 10 ( v in / v intercept ) (1) where: i d is the internally set detector current. v in is the input signal voltage. v intercept is the intercept voltage (that is, when v in = v intercept , the output voltage would be 0 v, if it were capable of going to 0 v).
ADL5519 rev. a | page 20 of 40 using the ADL5519 basic connections the ADL5519 is specified for operation up to 10 ghz. as a result, low impedance supply pins with adequate isolation between functions are essential. a power supply voltage between 3.3 v and 5.5 v should be applied to vpsa, vpsb, and vpsr. power supply decoupling capacitors of 100 pf and 0.1 f should be connected close to these power supply pins (see figure 53 ). the paddle of the lfcsp package is internally connected to comr. for optimum thermal and electrical performance, the paddle should be soldered to a low impedance ground plane. input signal coupling the ADL5519 inputs are differential but were characterized and are generally used single ended. when using the ADL5519 in single-ended mode, the inha, inhb pins must be ac-coupled, and inla, inlb must be ac-coupled to ground. suggested coupling capacitors are 47 nf, ceramic 0402-style capacitors for input frequencies of 1 mhz to 10 ghz. the coupling capacitors should be mounted close to the inha, inhb and inla, inlb pins. the coupling capacitor values can be increased to lower the input stage high-pass cutoff frequency. the high-pass corner is set by the input coupling capacitors and the internal 10 pf high-pass capacitor. the dc voltage on inha, inhb and inla, inlb is approximately one diode voltage drop below the supply voltage. vpsa 5pf 5pf 18.7k ? 18.7k ? 2k ? first gain stage offset comp inha inla a = 9db 0 6198-044 current gm stage figure 52. single-channel input interface although the input can be reactively matched, in general this reactive matching is not necessary. an external 52.3 shunt resistor (connected on the signal side of the input coupling capaci- tors, as shown in figure 53 ) combines with the relatively high input impedance to give an adequate broadband match of 50 . the coupling time constant, 50 c c /2, forms a high-pass corner with a 3 db attenuation at f hp = 1/(2 50 c c ), where c1 = c2 = c3 = c4 = c c . using the typical value of 47 nf, this high- pass corner is ~68 khz. in high frequency applications, f hp should be as large as possible to minimize the coupling of unwanted low frequency signals. in low frequency applications, a simple rc network forming a low-pass filter should be added at the input for similar reasons. this low-pass filter should generally be placed at the generator side of the coupling capacitors, thereby lowering the required capacitance value for a given high-pass corner frequency.
ADL5519 rev. a | page 21 of 40 06198-043 vpos vpsb c16 100pf c11 0.1f c5 0.1f c10 100pf vref adjb diff out+ diff out? ADL5519acpz exposed paddle temp sensor c8 100pf c15 0.1f clpa temp vpsr adja clpb vlvl vref adjb vpsb vsta vstb outb fbkb outn outp fbka outa vpsa c7 100pf vpsa c12 0.1f v ps r adja c9 100pf 27 28 29 30 31 32 inha pwdn c4 47nf c3 47nf inhb inlb comr pwdn inla inha inhb c2 47nf c1 47nf r6 52.3 ? r5 52.3 ? vlvl setpoint voltage b output voltage b setpoint voltage b output voltage b vpsa vpsb vpsr 25 26 3 4 5 6 7 8 1 2 comr comr comr comr 14 13 12 11 10 9 16 15 nc nc 22 21 20 19 18 17 24 23 comr comr figure 53. basic connections for operation in measurement mode
ADL5519 rev. a | page 22 of 40 temperature sensor interface the ADL5519 provides a temperature sensor output capable of driving 4 ma. the temperature scaling factor of the output voltage is ~4.48 mv/c. the typical absolute voltage at 27c is approxi- mately 1.36 v. tem p v ps r internal vptat 12k ? 4k? comr 06198-045 figure 54. temp interface simplified schematic vref interface the vref pin provides a highly stable voltage reference. the voltage on the vref pin is 1.15 v, which is capable of driving 3 ma. an equivalent internal resistance is connected from vref to comr for 3 ma sink capability. power-down interface the operating and stand-by currents for the ADL5519 at 27c are approximately 60 ma and less than 1 ma, respectively. to completely power down the ADL5519, the pwdn and adja, adjb pins must be pulled within 200 mv of the supply voltage. when powered on, the output reaches to within 0.1 db of its steady-state value in about 0.5 s; the reference voltage is avail- able to full accuracy in a much shorter time. this wake-up response time varies, depending on the input coupling network and the capacitance at the clpa, clpb pins. pwdn disables the outp, outn, vref, and temp pins. the power-down pin, pwdn, is a high impedance pin. the adja and adjb pins, when pulled within 200 mv of the supply voltage, disable outa and outb, respectively. setpoint interfacevsta, vstb the vsta, vstb inputs are high impedance (40 k) pins that drive inputs of internal op amps. the v set voltage appears across the internal 1.5 k resistor to generate a current, i set . when a portion of v out is applied to vsta, vstb, the feedback loop forces ? i d log 10 ( v in / v intercept ) = i set (2) if v set = v out /2x, then i set = v out /(2x 1.5 k). the result is v out = (? i d 1.5 k 2x) log 10 ( v in / v intercept ) i set v set v set 1.5k ? 20k? 20k? comm comm 06198-048 figure 55. vsta, vstb interface simplified schematic the slope is given by ?i d 2x 1.5 k = ?22 mv/db x. for example, if a resistor divider to ground is used to generate a v set voltage of v out /2, then x = 2. the slope is set to ?880 v/decade or ?44 mv/db. see the altering the slope section for additional information. output interfaceouta, outb the outa, outb pins are driven by a push-pull output stage. the rise time of the output is limited mainly by the slew on clpa, clpb. the fall time is an rc-limited slew given by the load capaci- tance and the pull-down resistance at outa, outb. there is an internal pull-down resistor of 1.6 k the resistive load at outa, outb can be placed in parallel with the internal pull- down resistor to reduce the discharge time. outa, outb can source greater than 10 ma. outa, outb v psa, vpsb clpa, clpb 1.2k ? 400 ? comr 06198-049 figure 56. outa, outb inte rface simplified schematic
ADL5519 rev. a | page 23 of 40 difference outputoutp, outn the ADL5519 incorporates two operational amplifiers with rail-to- rail output capability to provide a channel difference output. as in the case of the output drivers for outa, outb, the output stages have the capability of driving greater than 10 ma. outa and outb are internally connected through 1 k resistors to the inputs of each op amp. the vlvl pin is connected to the positive terminal of both op amps through 1 k resistors to provide level shifting. the negative feedback terminal is also made available through a 1 k resistor. the input impedance of vlvl is 1 k, and the input impedance of fbka, fbkb is 1 k. see figure 57 for the connections of these pins. outp v psr v lvl fbka comr outa outb outn vpsr vlvl fbkb comr outb outa 1k ? 1k ? 1k? 1k? 1k? 1k? 1k? 1k? 06198-050 figure 57. outp, outn inte rface simplified schematic if outp is connected to fbka, outp is given as outp = outa ? outb + vlvl (3) if outn is connected to fbkb, outn is given as outn = outb ? outa + vlvl (4) outa fbka fbkb outp outn outb 14 13 12 11 06198-051 figure 58. op amp connections (all resistors are 1 k 20%) in this configuration, all four measurements, outa, outb, outp, and outn, are available simultaneously. a differential output can be taken from outp ? outn, and vlvl can be used to adjust the common-mode level for an adc connection. this is convenient not only for driving a differential adc but also for removing any temperature variation on vlvl. description of characterization the general hardware configuratio n used for most of the ADL5519 characterization is shown in figure 59 . the signal sources used in this example are the e8251a from agilent technologies. the inha, inhb input pins are driven by agilent signal sources, and the output voltages are measured using a voltmeter. 0 6198-052 computer controller agilent 34970a meter/ switching ADL5519 characterization board outa outb outp outn vref temp ina inb ?3db signal source ?3db signal source figure 59. general characterization configuration basis for error calculations the input power and output voltage are used to calculate the slope and intercept values. the slope and intercept are calculated using linear regression over the input range from ?40 dbm to ?10 dbm. the slope and intercept terms are used to generate an ideal line. the error is the difference in measured output voltage compared to the ideal output line. this is a measure of the linearity of the device. refer to the device calibration section for more information on calculating slope, intercept, and error. error from the linear response to the cw waveform is not a measure of absolute accuracy because it is calculated using the slope and intercept of each device. however, error verifies the linearity and the effects of modulation on device response. similarly, at temperature extremes, error represents the output voltage variations from the 25c ideal line performance. data presented in the graphs is the typical error distribution observed during characterization of the ADL5519. pulse response of the ADL5519 is 6 ns/8 ns rise/fall times. for the fastest response time, the capacitance on outa, outb should be kept to a minimum. any capacitance on the output pins should be counterbalanced with an equal capacitance on the clpa, clpb pins to prevent ringing on the output.
ADL5519 rev. a | page 24 of 40 device calibration the measured transfer function of the ADL5519 at 2.2 ghz is shown in figure 60 . the figure shows plots of both output voltage vs. input power and calculated error vs. input power. as the input power varies from ?60 dbm to ?5 dbm, the output voltage varies from 1.7 v to about 0.5 v. v out2 p in1 p in2 p in (dbm) v out1 output voltage (v) error (db) ?60 ?50 ?40 ?30 ?20 0 10 06198-053 ?10 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 figure 60. transfer function at 2.2 ghz with calibration points because slope and intercept vary from device to device, board- level calibration must be performed to achieve the highest accuracy. the equation for output voltage can be written as v out = slope ( p in ? intercept ) (6) where: slope is the change in output voltage divided by the change in input power, p in , expressed in decibels (db). intercept is the calculated power at which the output voltage would be 0 v. note that an output voltage of 0 v can never be achieved. in general, calibration is performed by applying two known signal levels to the ADL5519 input and measuring the corre- sponding output voltages. the calibration points are generally chosen to be within the linear-in-db operating range of the device (see the specifications section for more details). calculation of the slope and intercept is accomplished using the following equations: slope = ( v out1 ? v out2 )/( p in1 ? p in2 ) (7) intercept = p in1 ? ( v out1 / slope ) (8) once slope and intercept are calculated, an equation can be written that calculates the input power based on the output voltage of the detector. p in ( unknown) = (v out1(measured) / slope ) + intercept (9) the log conformance error of the calculated power is given by error (db) = ( v out(measured) ? v out(ideal) )/ slope (10) figure 60 includes a plot of the error at 25c, the temperature at which the log amp is calibrated. note that the error is not 0 db over the full dynamic range. this is because the log amp does not perfectly follow the ideal v out vs. p in equation, even within its operating region. the error at the calibration points of ?35 dbm and ?11 dbm is equal to 0 db, by definition. figure 60 also shows error plots for the output voltage at ?40c and +85c. these error plots are calculated using the slope and intercept at 25c. this is consistent with calibration in a mass-production environment, where calibration over temperature is not practical. adjusting accuracy through choice of calibration points in some applications, very high accuracy is required at one power level or over a reduced input range. for example, in a wireless transmitter, the accuracy of the high power amplifier (hpa) is most critical at or close to full power. in applications like agc control loops, good linearity and temperature performance are necessary over a large input power range. the temperature crossover point (the power level at which there is no drift in performance from ?40c to ?80c) can be shifted from high power levels to midpower levels using the method shown in the temperature compensation adjustment section. this shift equalizes the temperature performance over the complete power range. the linearity of the transfer function can be equalized by changing the calibration points. figure 61 demonstrates this equalization by changing the cali- bration points used in figure 60 to ?46 dbm and ?22 dbm. this adjustment of the calibration points changes the linearity to greater than 0.25 db over a 50 db dynamic range at the expense of a slight decrease in linearity at power levels between ?40 dbm and ?25 dbm. calibration points should be chosen to suit the application at hand. in general, however, do not choose calibration points in the nonlinear portion of the log amp transfer function (greater than ?10 dbm or less than ?40 dbm, in this example). v out2 p in1 p in2 v out1 output voltage (v) error (db) ?60 ?50 ?40 ?30 ?20 0 10 06198-055 ?10 p in (dbm) 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 figure 61. dynamic range extension by choosing calibration points that are close to the end of the linear range, 2.14 ghz
ADL5519 rev. a | page 25 of 40 another way of presenting the error function of a log amp detector is shown in figure 62 . in this example, the decibel (db) error at hot and cold temperatures is calculated with respect to the output voltage at ambient. this is a key difference when compared to the previous plots, in which all errors have been calculated with respect to the ideal transfer function at ambient. 06198-056 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 output voltage (v) error (db) p in (dbm) figure 62. error vs. temperature with respect to output voltage at 25c, 2.14 ghz (removes transfer function nonlinearities at 25c) with this alternative technique, the error at ambient becomes, by definition, equal to 0 (see figure 62 ). this value would be valid if the device transfer function perfectly followed the ideal of the v out = slope (p in ? intercept) equation. however, because an rms amp, in practice, never perfectly follows this equation (especially outside of its linear operating range), this plot tends to artificially improve linearity and extend the dynamic range, unless enough calibration points are taken to remove the error. figure 62 is a useful tool for estimating temperature drift at a particular power level with respect to the (nonideal) output voltage at ambient. temperature compensation adjustment the ADL5519 temperature performance has been optimized to ensure that the output voltage has minimum temperature drift at ?10 dbm input power. the applied voltage for the adja and adjb pins for some specified frequencies is listed in table 4 . however, not all frequencies are represented in table 4 , and experimentation may be required. compensating the device for temperature drift by using adja, adjb allows for great flexibility. to determine the optimal adjust voltage, sweep adja, adjb at ambient and at the desired temperature extremes for a couple of power levels while monitoring the output voltage. the point of intersection determines the best adjust voltage. some additional minor tweaking may be required to achieve the highest level of tempera- ture stability. with appropriate values, a temperature drift error of typically 0.5 db over the entire rated temperature range can be achieved. table 4. recommended adja, adjb voltage levels frequency recommended adja, adjb voltage (v) 100 mhz 0.65, 0.7 900 mhz 0.6, 0.65 1.9 ghz 0.5, 0.55 2.2 ghz 0.48, 0.6 3.6 ghz 0.35, 0.42 5.8 ghz 0.58, 0.7 8 ghz 0.72, 0.82 proprietary techniques are used to compensate for the temperature drift. the absolute value of compensation varies with frequency and circuit board material. adja, adjb are high impedance pins. the applied adja, adjb voltages can be supplied from vref through a resistor divider. figure 63 shows a simplified schematic representation of the adja, adjb interface. v ref i comp v tadj comr adja, adjb ADL5519 comr 06198-057 figure 63. adja, adjb interface simplified schematic
ADL5519 rev. a | page 26 of 40 altering the slope as discussed in the setpoint interfacevsta, vstb section, the slope can readily be increased by scaling the amount of output voltage at outa, outb that is fed back to the setpoint interface, vsta, vstb. when the full signal from outa, outb is applied to vsta, vstb, the slope has a nominal value of ?22 mv/db. this value can be increased by including a voltage divider between the outa, outb and vsta, vstb pins, as shown in figure 64 . ADL5519 outa, outb v out r1 r2 vsta, vstb 06198-058 figure 64. external network to raise slope the approximate input resistance for vsta, vstb is 40 k. scaling resistor values should be carefully selected to minimize errors. keep in mind that these resistors also load the output pins and reduce the load-driving capabilities. equation 11 can be used to calculate the resistor values. ? ? ? ? ? ? ? ? = 1 22 d s r2'r1 (11) where: s d is the desired slope, expressed in millivolts/decibels (mv/db). r2' is the value of r2 in parallel with 40 k. for example, using r1 = 1.65 k and r2 = 1.69 k (r2' = 1.62 k), the nominal slope is increased to ?44 mv/db. when the slope is increased, the loop capacitor, clpa, clpb, may need to be raised to ensure stability and to preserve a chosen averaging time. the slope can be lowered by placing a voltage divider after the output pin, following standard practices. channel isolation isolation must be considered when using both channels of the ADL5519 at the same time. the two isolation requirements that should be considered are the isolation from one rf channel input to the other rf channel input and the isolation from one rf channel input to the other channel output. when using both channels of the ADL5519, care should be taken in the layout to isolate the rf inputs, inha and inhb, from each other. coupling on the pc board affects both types of isolation. in most applications, the designer has the ability to adjust the power going into the ADL5519 through the use of temperature- stable couplers and accurate temperature-stable attenuators of different values. when isolation is a concern, it is useful to adjust the input power so the lowest expected detectable power is not far from the lowest detectable power of the ADL5519 at the frequency of operation. the lowest detectable power point of the ADL5519 has little variation from part to part. this equalizes the signals on both channels at their lowest possible power level, which reduces the overall isolation requirements and possibly adds attenuators to the rf inputs of the device, reducing the rf channel input isolation requirements. measuring the rf channel input to the other rf channel input isolation is straightforward and is done by measuring the loss on a network analyzer from one input to the other input. the outcome is shown in the specifications section of the data sheet. note that adding an attenuator in series with the rf signal increases the channel input-to-input isolation by the value of the attenuator. the isolation between one rf channel input and the other channel output is a little more complicated. the easiest approach (which was used in this datasheet) to measuring this isolation is to have one channel set to the lowest power level it is expected to have on its input (approximately ?50 dbm in this data sheet) and then increasing the power level on the other channel input until the output of the low power channel changes by 22 mv. because ?50 dbm is in the linear region of the detector, 22 mv equates to a 1 db change in the output. if the inputs to both rf channels are at the same frequency, the isolation also depends on the phase shift between the rf signals put into the ADL5519. this relationship can be demonstrated by placing a high power signal on one rf channel input and a low power signal slightly offset in frequency to the other rf channel. if the output of the low power channel is observed with an oscilloscope, it has a ripple that looks similar to a full-wave rectified sine wave with a frequency equal to the frequency difference between the two channels, that is, a beat tone. the magnitude of the ripple reflects the isolation at a specific phase offset (note that two signals of slightly different frequencies act like two signals with a constantly changing phase), and the frequency of that ripple is directly related to the frequency offset. the data shown in the specifications section assumes worst-case amplitude and phase offset. if the rf signals on channel a and channel b are at significantly different frequencies, the input-to- output isolation increases, depending on the capacitors placed on clpa, clpb and the frequency offset of the two signals, due to the response roll-off within the ADL5519.
ADL5519 rev. a | page 27 of 40 output filtering package considerations accurate power detection for signals with rf bursts is achieved when the ADL5519 is able to respond quickly to the change in rf power. for applications in which maximum video bandwidth and, consequently, fast rise time are desired, it is essential that the clpa, clpb pins have very little capacitance on them (some capacitance reduces the ringing). the ADL5519 uses a compact, 32-lead lfcsp. a large exposed paddle on the bottom of the device provides both a thermal benefit and a low inductance path to ground for the circuit. to make proper use of this packaging feature, the pcb rf/dc common-ground reference needs to make contact with the paddle with as many vias as possible to lower inductance and thermal impedance. the nominal output video bandwidth of 10 mhz can be reduced by connecting a ground-referenced capacitor (c flt ) to the clpa, clpb pins, as shown in figure 65 . this is generally done to reduce output ripple (at twice the input frequency for a symmetric input waveform, such as a sinusoidal signal). operation above 8 ghz the ADL5519 is specified for operation up to 8 ghz, but it provides useful measurement accuracy over a reduced dynamic range of up to 10 ghz. figure 66 shows the performance of the ADL5519 over temperature for a input frequency of 10 ghz. this high frequency performance is achieved using the configuration shown in figure 53 . the dynamic range shown is reduced from the typical device performance, but the ADL5519 can provide 30 db of measurement range with less than 3 db of linearity error. i loga, i logb c flt 1.5k ? outa, outb clpa, clpb 3.5pf ADL5519 +4 0 6198-059 implementing an impedance match for frequencies greater than 8 ghz can improve the sensitivity of the ADL5519 and its measure- ment range. figure 65. lowering the po st demodulation bandwidth c flt is selected using the following equation: 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 4.0 3.0 2.0 1.0 0 ?1.0 ?2.0 ?3.0 ?4.0 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 output voltage (v) error (db) p in (dbm) 06198-169 pf5.3 k5.1 1 u:us bandwidth video c flt (12) the video bandwidth should typically be set to a frequency less than or equal to approximately 1/10 the minimum input frequency. there are no problems with putting large capacitor values on the clpa, clpb pins. these large capacitor values ensure that the output ripple of the demodulated log output, which is at twice the input frequency, is well filtered. signals with modulation may need additional filtering (a larger c flt capacitance) to remove modulation bleedthrough. figure 66. v out and log conformance vs. input amplitude at 10 ghz, over temperature, adja, adjb = 1.8 v, 1.8 v
ADL5519 rev. a | page 28 of 40 applications information measurement mode the ADL5519 is placed in measurement mode by connecting outa, outb to vsta, vstb, respectively. the part has an offset voltage, a negative slope, and a v outa, v outb measurement inter- cept at the high end of its input signal range. the output voltage vs. input signal voltage of the ADL5519 is linear-in-db over a multidecade range. the equation for this function is of the following form: v out = x v slope/dec log 10 ( v in / v intercept ) = (13) x v slope/db 20 log 10 ( v in / v intercept ) (14) where: x is the feedback factor in v set = v out / x . v slope/dec is nominally ?440 mv/decade or ?22 mv/db. v intercept is the x-axis intercept of the linear-in-db portion of the v out vs. v in curve. v intercept is 2 dbv for a sinusoidal input signal. an offset voltage, v offset , of 0.45 v is internally added to the detector signal so that the minimum value for v out is x v offset . if x = 1, the minimum v out value is 0.45 v. the slope is very stable vs. process and temperature variation. when base-10 logarithms are used, v slope/dec represents the volts/decade. a decade corresponds to 20 db; v slope/dec /20 = v slope/db represents the slope in v/db. as noted in equation 13 and equation 14, the v out voltage has a negative slope. this is also the correct slope polarity to control the gain of many vgas in a negative feedback configuration. because both the slope and intercept vary slightly with frequency, see the specifications section for application-specific values for slope and intercept. although demodulating log amps respond to input signal voltage and not input signal power, it is customary to discuss the amplitude of high frequency signals in terms of power. in this case, the characteristic impedance of the system, z 0 , must be known to convert voltages to their corresponding power levels. the following equations are used to perform this conversion: p (dbm) = 10 log 10 ( v rms 2 /( z 0 1 mw)) (15) p (dbv) = 20 log 10 ( v rms /1 v rms ) (16) p (dbm) = p (dbv) ? 10 log 10 ( z 0 1 mw/1 v rms 2 ) (17) for example, p intercept , for a sinusoidal input signal expressed in terms of dbm (decibels referred to 1 mw), in a 50 system is p intercept (dbm) = p intercept (dbv) ? 10 log 10 ( z 0 1 mw/1 v rms 2 ) = 2 dbv ? 10 log 10 (50 10 ?3 ) = 15 dbm for a square wave input signal in a 200 system p intercept (dbm) = ?1 dbv ? 10 log 10 [(200 1 mw/1 v rms 2 )] = +6 dbm more information about the intercept variation dependence upon waveform can be found in the ad8313 and ad8307 data sheets. as the input signals to channel a and channel b are swept over their nominal input dynamic range of ?5 dbm to ?55 dbm, the output swings from 0.5 v to 1.6 v. the voltages of outa, outb are also internally applied to a difference amplifier with a gain of 1. when the input power is swept, outp swings from approxi- mately 0.5 v to 1.75 v, and outn swings from 1.75 v to 0.5 v. the vlvl pin sets the common-mode voltage for outp, outn. an output common-mode voltage of 1.15 v can be set using a resistor divider between the vref and vlvl pins. measurement of large differences between inha, inhb can be affected by on-chip signal leakage. controller mode in addition to being a measurement device, the ADL5519 can also be configured to set and control signal levels. each of the two log detectors can be separately configured to set and control the output power level of a vga or variable voltage attenuator (vva). see the controller mode section of the ad8317 datasheet for more information on running a single channel in controller mode. alternatively, the two log detectors can be configured to measure and control the gain of an amplifier or signal chain. the channel difference outputs can be used to control a feedback loop to the ADL5519 rf inputs. a capacitor connected between fbka and outp forms an integrator, keeping in mind that the on-chip 1 k feedback resistor forms a 0. (the value of the on-chip resistors can vary as much as 20% with manufacturing process variation.) if channel a is driven and channel b has a feedback loop from outp through a vga, outp integrates to a voltage value such that outb = ( outa + vlvl )/2 (18) the output value from outn may or may not be useful. it is given by outn = 0 v (19) for vlvl < outa/3. otherwise, outn = (3 vlvl ? outa )/2 (20)
ADL5519 rev. a | page 29 of 40 if vlvl is connected to the outa pin, outb is forced to equal outa through the feedback loop. this flexibility provides the capability to measure one channel operating at a given power level and frequency while forcing the other channel to a desired power level at another frequency. the voltages applied to the adja, adjb pins should be selected carefully to minimize temperature drift of the output voltage. the temperature drift is the statistical sum of the drift from channel a and channel b. as stated previously, vlvl can be used to force the slaved channel to operate at a different power from the other channel. if the two channels are forced to operate at different power levels, some static offset occurs due to voltage drops across metal wiring in the ic. if an inversion is necessary in the feedback loop, outn can be used as the integrator by placing a capacitor between outn, outp. this changes the output equation for outb and outp to outb = 2 outa ? vlvl (21) for vlvl < outa/2, outn = 0 v (22) otherwise, outn = 2 vlvl ? outa (23) equation 18 to equation 23 are valid when channel a is driven and channel b is slaved through a feedback loop. when channel b is driven and channel a is slaved, these equations can be altered by changing outb to outa and outn to outp.
ADL5519 rev. a | page 30 of 40 automatic gain control figure 67 shows how the ADL5519 can be connected to provide automatic gain control to an amplifier or signal chain. additional pins are omitted for clarity. in this configuration, both detectors are connected in measurement mode with appropriate filtering being used on clpa, clpb to provide adequate filtering of the demodulated log output. outa, however, is also connected to the vlvl pin of the on-board difference amplifier. in addition, the outp output of the difference amplifier drives a variable gain element (either vva or vga) and is connected back to the fbka input via a capacitor so that it is operating as an integrator. assume that outa is much bigger than outb. because outa also drives vlvl, this voltage is also present on the noninverting input of the op amp driving outp. this results in a current flow from outp through the integrating capacitor into the fbka input. this results in the voltage on outp increasing. if the gain control transfer function of the vga/vva is positive, this increases the gain, which in turn increases the input signal to inha. the output voltage on the integrator continues to increase until the power on the two input channels is equal, resulting in a signal chain gain of unity. if a gain other than 0 db is required, an attenuator can be used in one of the rf paths, as shown in figure 67 . alternatively, power splitters or directional couplers of different coupling factors can be used. another convenient option is to apply a voltage on vlvl other than outa. refer to equation 18 and the controller mode section for more detail. if the vga/vva has a negative gain control sense, the outn output of the difference amplifier can be used with the integrating capacitor tied back to fbkb. alternatively, the inputs could be swapped. the choice of the integrating capacitor affects the response time of the agc loop. small values give a faster response time but may result in instability, whereas larger values reduce the response time. capacitors that are too large can also cause oscillations due to the capacitive drive capability of the op amp. in automatic gain control, the capacitors on clpa and clpb, which perform the filtering of the demodulated log output, must still be used and also affect loop response time.
ADL5519 rev. a | page 31 of 40 0 6198-063 channel a log detector channel b log detector clpb clpa vlvl inhb inlb inla inha vsta vstb outb fbkb outn outp fbka outa ADL5519 c int diff out + attenuator vga/vva 0.1f 0.1f 50? 50? 0.1f 0.1f directional or power splitter directional or power splitter figure 67. operation in controller mode for automatic gain control
ADL5519 rev. a | page 32 of 40 gain-stable transmitter/receiver there are many applications for a transmitter or receiver with a highly accurate temperature-stable gain. for example, a multi- carrier, base station high power amplifier (hpa) using digital predistortion can have a power detector and an auxiliary receiver. the power detector and all parts associated with it can be removed if the auxiliary receiver has a highly accurate temperature-stable gain. with a set gain receiver, the adc on the auxiliary receiver can determine not only the overall power being transmitted but also the power in each carrier for a multicarrier hpa. without the use of a detector, the auxiliary receiver is very difficult to calibrate accurately over temperature due to the part-to-part variation of the components in the auxiliary receiver. in controller mode, the ADL5519 can be used to hold the receiver gain constant over a broad input power/temperature range. in this application, the difference outputs are used to hold the receiver gain constant. figure 69 shows an example of how this can be done. the rf input is connected to inhb, using a 19 db coupler, and the down-converted output from the signal chain is connected to inha, using a 19 db coupler. a 100 pf capacitor is connected between fbka and outp, forming an integrator. outa is connected to vlvl, forcing outp to adjust the vga so that outb is equal to outa. the circuit gain is set by the difference in the coupling values of the input and output couplers and the differences in path losses to the detector. because they are operating at different frequencies, the appropriate voltages on the adja, adjb pins must be supplied. adja is set to 0.6 v and adjb is set to 0.65 v to set the ?40 o c/+85 o c crossover point toward the center of the input power range. using the suggested adja value for 80 mhz would put the crossover point at a higher power level. figure 68 shows the results of the circuit in figure 69 . the input power is swept from ?47 dbm to +8 dbm. the output power is measured, and the gain is calculated at +25c, ?40c and +85c. with equal valued couplers used on the input and output, the expected gain is about 0 db. due to path loss differences and differences due to using two separate frequencies, the average gain is about 2.5 db. in this configuration, approximately 50 db of control range with 0.2 db drift over temperature is obtained. for an auxiliary receiver, less than 5 db of variation is expected over temperature. if the power levels are chosen to coincide with the temperature crossover point, approximately 0.1 db of temperature variation can be expected. most of the gain change over input power level is caused by performance differences at different frequencies. 4.0 1.5 2.0 2.5 3.0 3.5 1.0 0.5 0 ?50 ?40 ?30 ?20 ?10 0 10 gain (db) p in (dbm) 06198-171 gain +25c gain ?40c gain +85c figure 68. performance of gain-stable receiver
ADL5519 rev. a | page 33 of 40 100pf 100pf 0.1uf outb temp fbkb vpsr vref clpb clpa outa fbka outn outp vlvl inla pwdn comr inhb inha adja vpsa adjb vstb vsta vpsb inlb 47nf exposed paddle c1 10 19 11 20 5 7 18 1514 12 13 6 26 2829 3132 25 21 22 3 4 8 17 2 1 16 9 24 23 27 30 ADL5519 c9 5v c12 c7 5v 100pf 0.1uf c15 c8 power down b channel out temperature sensor out 0.1uf v ref c10 47nf c3 47nf c2 c16 c11 47nf c4 52.3 r30 52.3 r31 0.6v 0.1 uf 0.1 uf diff out? mode sel 0v to 1.2v 90mhz lpf rfin 900mhz 0 ? 0 ? 454 ? ifout 80mhz 19db coupling 19db coupling 0 ? 0 ? 454 ? ad8342 adl5330 100 pf 0.65v 820mhz 06198-172 figure 69. gain-stable receiver circuit
ADL5519 rev. a | page 34 of 40 measuring vswr measurement of reflected power in wireless transmitters is a critical auxiliary function that is often overlooked. the power reflected back from an antenna is specified using either the voltage standing wave ratio (vswr) or the reflection coefficient (also referred to as the return loss). poor vswr can cause shadowing in a tv broadcast system because the signal reflected off the antenna reflects again off the power amplifier and is then rebroadcast. in wireless communications systems, shadowing produces multipath- like phenomena. poor vswr can degrade transmission quality; the catastrophic vswr that results from damage to a co-axial cable or to an antenna can, at its worst, destroy the transmitter. the ADL5519 delivers an output voltage proportional to the log of the input signal over a large dynamic range. a log-responding device offers a key advantage in vswr measurement applications. to compute gain or reflection loss, the ratio of the two signal powers (either output/input or reverse/forward) must be calculated. an analog divider must be used to perform this calculation with a linear-responding diode detector, but only simple subtraction is required when using a log-responding detector (because log(a/b) = log(a) ? log(b)). a dual rf detector has an additional advantage compared to a discrete implementation. there is a natural tendency for two devices (rf detectors, in this case) to behave similarly when they are fabricated on a single piece of silicon, with both devices having similar temperature drift characteristics, for example. at the summing node, this drift cancels to yield a result that is more temperature stable. in figure 71 , two directional couplers are used, one to measure forward power and one to measure reverse power. additional attenuation is required before applying these signals to the detectors. the ADL5519 dual detector has a measurement range of 50 db in each detector. care must be taken in setting the attenua- tion levels so the reflection coefficient can be measured over the desired output power range. the level planning used in this example is graphically depicted in figure 70 . in this example, the expected output power range from the hpa is 30 db, from 20 dbm to 50 dbm. over this power range, the ADL5519 can accurately measure reflection coefficients from 0 db (short, open, or load) to ?20 db. each ADL5519 detector has a nominal input range from ?5 dbm to ?55 dbm. in this example, the maximum forward power of +50 dbm is attenuated to ?10 dbm at the detector input (this attenuation is achieved through the combined coupling factor of the directional coupler and the subsequent attenuation). this puts the maximum power at the detector comfortably within its linear operating range. also, when the hpa is transmitting at its lowest power level of +20 dbm, the detector input power is ?40 dbm, which is still within its input operating range. 0 6198-075 50dbm 40dbm 30dbm 20dbm 10dbm 0dbm ?10dbm ?20dbm ?30dbm ?40dbm ?50dbm ?60dbm forward power range power at input a reverse power range powr at input b 55db attenuation dector a/b input range 60db attenuation figure 70. ADL5519 vswr level planning careful level planning should be used to match the input power levels in a dual detector and to place these power levels within the linear operating range of the detectors. the power from the reverse path is attenuated by 55 db, which means that the detector is capable of measuring reflected power up to 0 db. in most appli- cations, the system is designed to shut down when the reflection coefficient degrades below a certain minimum (for example, 10 db). full reflection is allowed when using the ADL5519 because of its large dynamic range. in the case of very little reflection (a return loss of 20 db) and the hpa is transmitting +20 dbm, the reverse path detector has an input power of ?55 dbm. the application circuit in figure 71 provides a direct reading of return loss, forward power, and reverse power. if the forward and reverse phase difference (phase angle) is needed to optimize the power delivered to the antenna, the ad8302 should be used. it provides one output that represents the return loss and one output that represents the phase difference between the two signals. however, the ad8302 does not provide the absolute forward or reverse power.
ADL5519 rev. a | page 35 of 40 06198-074 channel a log detector channel b log detector vstb vsta inha inhb outb fbkb outn outp fbka outa bias temp outa outb ADL5519 adc adc adc microprocessor/ dsp forward power reverse power return loss hpa p out = 20dbm to 50db m 40db 35db 20db 20db 0.1f 52.3 ? 0.1f 52.3 ? p in = ?10dbm to ?40dbm p in = ?5dbm to ?55dbm figure 71. ADL5519 configuration for measuring reflection coefficients
ADL5519 rev. a | page 36 of 40 evaluation board configuration options table 5. evaluation board (rev. a) configuration options component description default conditions vpos, vpsb, vpsr, gnd, gnd1, gnd3 supply and ground connections. vpos, vpsb, and vpsr are internally connected. gnd, gnd1, and gnd3 are internally connected. not applicable r0a, r0b, r5, r6, r30, r31, c1, c2, c3, c4 input interface. the 52.3 resistors in the r30 and r 31 positions combine with the ADL5519 internal input impedance to give a br oadband input impedance of about 50 . c1, c2, c3, and c4 are dc-blocking capacitors. a reactive impedance match can be implemented by replacing r5, r6, r 30, and r31 with an inductor and by replacing c1, r0a and c4, r0b with appropriately valued capacitors. r30, r31 = 52.3 (size 0402), c1 to c4 = 47 nf (size 0402) r0a, r0b = 0 r5, r6 = open r14 temperature sensor interface. temperature sensor output voltage is avai lable at the test point labeled temp. r14 can be used as a pull-down resistor. r14 = open (size 0603) r13, r17, r18, r19, r27, r28, r29 temperature compensation interface. a voltage source at adja, adjb can be used to optimize the temperature performance for various input frequencies. the pads for r27/r28 or r27/r29 can be used for voltage dividers from the vre f node to set the adja, adjb voltages at different frequencies. the individual log channels can be disabled by installing 0 resistors at r18 and r19. r13, r17, r18, r19, r28, r29 = open (size 0603) r27 = 0 (size 0603) r8, r12, r15, r16, r20, r21, r22, r23, c13, c14 output interface, measurement mode. in measurement mode, a portion of the output voltage is fed back to vsta, vstb via r8, r12. the magnitude of the slope of the outa, outb output voltage response can be increased by reducing the portion of v outa , v outb that is fed back to vsta, vstb. the slope can be decreased by implementing a voltage divider by using r20 and r16 or r21 and r15. r20 and r21 ca n also be used as a back-terminating resistor or as part of a single-pole, low-pass filter. r8, r12 = 0 (size 0603) r15, r16, r22, r23 = open (size 0603) c13, c14 = open (size 0603) r20, r21 = 200 (size 0603) r8, r12, r22, r23 output interface, controller mode. in this mode, the 0 resistors must be removed, leaving r8 and r12 open. in controller mode, the ADL5519 can control the gain of an external component. a setpoint voltage is applied to vsta, vstb, the value of which corresponds to the desired rf input signal level applied to the corresponding ADL5519 rf input. a sample of the rf output signal from th is variable-gain component is selected, typically via a directional coupler, and applied to ADL5519 rf input. the voltage at outa, outb is applied to the gain contro l of the variable gain element. a control voltage is applied to vsta, vstb. the magnitude of the control voltage can optionally be attenuated via the voltag e divider comprising r8, r12 and r22, r23; or a capacitor can be installed in the r22, r23 position to form a low-pass filter along with r8, r12. r8, r12, r22, r23 = open (size 0603) r3, r4, r11, r24, r25, r26, c7, c8, c11, c12, c15, c16 power supply decoupling. the nominal supply decoupling consists of a 100 pf filter capacitor placed physically close to the ADL5519 and a 0.1 f capacitor placed nearer to each power supply input pin. r3, r4, r11, r24, r25, r26 = 0 (size 0603) c7, c8, c11 = 100 pf (size 0603) c12, c15, c16 = 0.1 f (size 0603) r1, r2, r9, r10 output interface, difference. r9 and r10 can be replaced with a capacitor to form an integrator for constant gain controller mode r1, r2, r9, r10 = 0 (size 0603) c9, c10 filter capacitor. the low-pass corner frequency of the circuit that drives outa, outb can be lowered by placing a capacitor between clpa, clpb and ground. increasing this capacitor increases the overall rise/fal l time of the ADL5519 for pulsed input signals. see the output filtering section for more details. c9, c10 = 1000 pf (size 0603) r7, c6 vlvl interface. vref can be used to drive vlvl through a voltage divider formed using r7 and c6. r7 = open (size 0603) c6 = open (size 0603)
ADL5519 rev. a | page 37 of 40 evaluation board schematic and artwork 06198-068 52.3 r0402 agnd agnd 52.3 r0402 47nf c0402 100pf 0.1uf agnd open r0603 r0603 testloop testloop r0603 0 r0603 0 agnd open r0603 agnd open r0603 testloop black testloop black testloop agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd 47nf c0402 47nf c0402 agnd agnd agnd agnd agnd 0 r0603 0.1 uf c0603 agnd agnd 1000pf c0603 testloop black smasm t open c0603 open c0603 open c0603 smasm t testloop sm asm t smasmt testloop smasmt smasmt r0603 smasm t smasmt r0603 r0603 r0603 0 r0603 open r0603 open r0603 r0603 r0603 open r0603 smasm t r0603 0 testloop r0603 open r0603 100pf 0.1uf open open open open 100pf 0.1uf hta_csp5x5_gnd 1000pf c0603 agnd outb temp fbkb vpsr vref clpb clpa outa fbka outn outp vlvl inla pwdn comr inhb inha adja vpsa adjb vstb vsta vpsb inlb open r0402 sm asm t sm asm t 0 ohm c0402 0 ohm c0402 open r0402 47nf c0402 32lfcsp5x5 inha c1 r6 r0b r0a inhb inha r5 vsta 10 19 11 20 5 7 18 15 14 12 13 6 26 28 29 3132 25 21 22 3 4 8 17 2 1 16 9 24 23 27 30 z1 ADL5519 adjb vref vlvl temp c9 adja pwdn vstb z2 c15 c0402 c8 c0402 r17 r0402 r0402 r19 vpsb r13 r0402 r18 r0402 0 r4 r0402 r3 0 r0402 c12 c0402 c7 c0402 vref adjb adja r28 r7 open vpsb vpsr vpsb red r26 vpsa vpsr vpsa pwdn r14 0 r12 r21 r16 r15 r2 0 r8 0 r9 r20 200 200 outb outb outa outa 0 r10 vst a adja temp red vstb a djb vref red outn c13 c14 c6 outp outp outn gnd1 c10 c5 r1 c3 c2 red vlvl gnd2 gnd3 r22 r23 r24 r25 red vpos vpos red vpsr 0 r27 r29 c0402 c16 c0402 c11 r0402 0 r11 c4 r30 inhb r31 figure 72. evaluation board schematic
ADL5519 rev. a | page 38 of 40 06198-069 figure 73. top side layout 06198-070 figure 74. top side silkscreen 06198-071 figure 75. bottom side layout 06198-072 figure 76. bottom side silkscreen
ADL5519 rev. a | page 39 of 40 outline dimensions 032807-a compliant to jedec standards mo-220-vhhd-2 1 32 8 9 25 24 17 16 2.85 2.70 sq 2.55 top view coplanarity 0.08 3.50 ref 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.20 min exposed pad (bot tom view) pin 1 indicator 0.30 0.25 0.18 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom seating plane 0.50 0.40 0.30 5.00 bsc sq 4.75 bsc sq figure 77. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad lead (cp-32-8) dimensions shown in millimeters ordering guide model temperature range packag e description package option ADL5519acpz-r7 1 ?40c to +125c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-8 ADL5519acpz-r2 1 ?40c to +125c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-8 ADL5519acpz-wp 1 , 2 ?40c to +125c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-8 ADL5519-evalz 1 evaluation board 1 z = rohs compliant part. 2 wp = waffle pack.
ADL5519 rev. a | page 40 of 40 notes ?2008C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06198-0-4/09(a)

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